Most conventional low-voltage integrated circuit processes are incapable of monolithically integrating a variety of parasitic-free high-voltage devices needed to fabricate circuits controlling high-voltage loads, particularly when a high-voltage push-pull (source-sink) output stage is required.
At least four isolation techniques (self isolation, RESURF junction isolation, conventional junction isolation and dielectric isolation) have been used in the prior art to achieve high voltage isolation for power integrated circuits. Baliga briefly reviews the characteristics of each of these techniques in I.E.E.E. Trans. on Electron Devices ED-33 1936 (1986).
Self isolation ("SI") uses a reverse biased junction between the source-drain regions and a common body region to obtain isolation. In one version relating to a class of CMOS devices, shown in FIG. 1, a p- substrate serves as the body region for one or more n-channel field effect transistors, with two n+ islands in the p substrate forming the source and drain of each NMOS transistor and with two p+islands in an n-well forming each PMOS transistor. Where the substrate doping is light (dopant concentration .ltoreq.3.times.10.sup.14 cm.sup.-3) to facilitate high-voltage breakdowns, the low-voltage NMOS transistor may require diffusion to form a P.sub.body, to make voltage breakdown thresholds over 0.8 V available and to avoid punchthrough breakdowns between source and drain regions. A P.sub.body region in an NMOS transistor is a p type region of moderate doping concentration that surrounds the source region in order to increase source-drain voltage breakdown threshold. High-voltage n-channel devices are fabricated using lightly doped n- drift region adjacent to the drain to provide field shaping; this also uses a technique known as lateral charge control, where the drift charge dose is approximately 10.sup.12 cm.sup.-2. Although the drain of each high-voltage NMOS device must be surrounded by an n-drift region, it is optional whether the gate and source also surround the drain and form a familiar "annular device" well described in the literature. As used herein, the term "annular region" refers to a three-dimensional region that is cylindrically shaped, where the cylinder cross-section is not necessarily circular. The high voltage n-channel MOS transistor typically employs a P.sub.body diffusion region, producing a lateral DMOS transistor. A DMOS transistor is formed by two consecutive diffusions of dopants of opposite electrical conductivity type (for example, first p type dopant, then n type dopant) in a region of semiconductor material; this produces two adjacent regions of different conductivity type that are used to control current in the transistor. A lateral MOS transistor, as shown in FIG. 1, is one in which charged particle flow from source to drain, or from drain to source, is substantially horizontal. An LDMOS transistor is a DMOS transistor in which current is substantially lateral. A self-isolation process allows the monolithic integration of low voltage (&lt;20 V) CMOS devices and high-voltage (60 V to 1000 V) n-channel lateral DMOS devices used for current sinking as a voltage pull-down device.
High voltage PMOS devices can be implemented by inclusion of additional process steps to provide a high-voltage pull-up device and to achieve high voltage source-sink output capability. FIG. 2A shows how the addition of a p-drift region extension on a PMOS device, fabricated in an n-well, can be used to integrate a high voltage PMOS device into architecture produced by an SI process architecture. Provided that the p substrate is doped considerably lighter than the diffused n-well region, punchthrough breakdown from drain to substrate is avoided. Inclusion of an n+ buried layer, as shown in FIG. 2B, may eliminate voltage snap back, whereby bipolar transistor breakdown voltage BV.sub.ceo is abruptly lowered, substrate current is increased and the chances for device failure or destruction are increased. Inclusion of the n+ buried layer in FIG. 2B degrades the .beta. parameter for current gain of the vertical parasitic substrate pnp; but this introduces a diode breakdown mechanism between the p+ drain and the n+buried layer. For reasonable epitaxial layer thicknesses (.congruent.15 to 20 .mu.m) and reasonable diffusion times so that the buried n+ layer connects with the n-well region, this diode breakdown is restricted to voltages above 200 V.
RESURF Junction Isolation or JIR, which is another high voltage process (see FIG. 3), achieves high breakdown voltages (60 to 1200 V) in an n-channel device by forming a lateral charge control region that has a charge density .congruent.10.sup.12 cm.sup.-2 adjacent to a thin (5-8 .mu.m) n- epitaxial layer. The n- epi layer forms a drift region analogous to the implanted lightly doped drain region in an SI process. Because this process is carried out epitaxially using a common n- layer on a p substrate, p+ isolation is required to separate the NMOS drain from other devices. Because the epitaxial layer is thin, isolation is easily accomplished with a single down-isolation diffusion. In a down-isolation (up-isolation) diffusion, rapidly diffusing dopant, B or Al for p type dopant and P for n type dopant, is introduced in a thin deposit at the top (bottom) of a layer of semiconductor material, and the dopant is allowed to diffuse vertically downward (upward) into the layer adjacent to the dopant deposit. This structure was introduced by Appels and Vaes in "High Voltage Thin Layer Devices." IEDM Tech Digest, pp. 230-241 (1979). The charge control region redistributes the surface electric field; hence its name "reduced-surface field" (RESURF). As with an SI n-channel MOS device with lightly doped drain, the maximum voltage of a device produced with JIR is determined by the n+ drain to p substrate breakdown voltage; this voltage can be made high if a lightly doped p substrate is used. The breakdown voltage of the NMOS device is selected by the gate-to-drain distance, as with an SI device with lightly doped drain; no process alteration is required to vary this breakdown voltage, provided the voltage is less than the n+ drain to p substrate breakdown voltage.
To avoid punchthrough breakdown or parasitic bipolar action in low voltage CMOS areas, an n+ buried layer and (optional) sinker are employed. PMOS devices are fabricated in the n- epitaxial layer, and NMOS devices are constructed in a diffused p-well that is surrounded by the n+ buried layer and sinker. The p-well is disconnected electrically from the substrate when it is desirable. Otherwise, the p-well containing the NMOS device may contact the p substrate.
Because the epi layer is lightly doped to form an n- charge control region, monolithic integration of a high-voltage PMOS device is severely limited by punchthrough breakdown and by parasitic pnp transistor snap back. FIG. 4A illustrates that formation of the high-voltage PMOS source produces a parasitic diode D1, which requires separation by a full drift length L.sub.d of the n+ contact from the p+ isolation region to prevent avalanche. The structure of FIG. 4A also has a parasitic bipolar transistor Q1 associated with the source; this transistor will punch through to the substrate in the presence of less than 60 V bias. The drain also exhibits this punchthrough effect with a parasitic transistor Q2; and Q2 will exhibit a super-beta (very high current gain) pnp characteristic that has very low snap back voltage due to low breakdown voltage threshold BVce.sub.o. Addition of the n+ buried layer shown in FIG. 4B eliminates Q1 and Q2, but this requires a newly formed diode D3 connected from p+ source to n+ buried layer diode to support a high voltage supply ,without avalanching. Due to the presence of the thin epi layer, the high voltage Supply is restricted to voltage differences below 100 V at best. Use of a thicker epi layer requires use of deeper p+ isolation diffusions and deeper sinker diffusions and eliminates many of the cost benefits of JIR.
Scaling JIR to thicker dimensions may also require increase of the drift charge beyond the maximum charge allowed by JIR. This scaling process is known as conventional junction-isolation (JIC) and is illustrated in FIG. 5. A thick n- epi layer (typically 8 to 50 .mu.m thickness) is grown over a p substrate and is isolated by p+ isolation regions as shown. Using a rapidly diffusing p type dopant, such as boron or aluminum, the p+ isolation may be achieved: (1) by using a single down-isolation diffusion directed vertically downward into an epi layer; or (2) by using a buried layer together with an up-isolation diffusion, directed vertically upward into the epi layer from the bottom, and a down-isolation diffusion, directed vertically downward from the top surface of the epi, where the two diffusing dopant profiles meet and merge within the epi layer and form a single wrap-around isolation region that extends from the buried layer upward to the top surface of the epi layer. A wrap-around isolation region is annular region of semiconductor material, heavily doped of one electrical conductivity type, that laterally surrounds a region of semiconductor material of a second electrical conductivity type that is to be electrically isolated from semiconductor material that lies outside a cylinder defined by the annular region. For net epi layer thicknesses beyond 30 .mu.m, the epi growth is sometimes split into two steps, with an additional mid-isolation diffusion mask and implant included between the upper and lower epi layers to form an up-, middle- and down-isolation regions. Low voltage logic is formed in an isolated n- epi region, with a low voltage PMOS device being formed directly in the n- epi material and a low-voltage NMOS device being formed in a diffused p-well. An optional n+ buried layer, formed by introducing a slowly diffusing material such as antimony or arsenic at the substrate-epi layer junction, may be used to suppress parasitic substrate bipolar action. This buried layer is also used to reduce the resistance of the drain region of a high voltage lateral device in the on-state, or of a vertical DMOS region formed by the inclusion of a P.sub.body diffusion region that is self-aligned to the polysilicon gate. In such devices, the n- epi layer serves as the drain region and has an n+ contact region on its surface. The n+ source region in such a device is enclosed totally by a deeper P.sub.body region and must be surrounded at the surface on all sides either by the polysilicon gate or by the p+ region. Although vertical DMOS transistor action is possible in this situation, device action is lateral in the sense that current is collected by a drain contact on the surface of the device. An optional n+ sinker may be included to connect the drain contact at the top to the n+buried layer and to further reduce resistance.
FIG. 6 shows a high-voltage PMOS transistor with lightly doped drain (p-) integrated into JIC using p+ up-isolation and down-isolation regions that laterally surround the device. To prevent punchthrough and parasitic. substrate PNP snap back (which prevented high voltage PMOS integration into the RESURF process), the JIC process uses a slowly diffusing n+ dopant to form a buried layer and a faster diffusing n+ dopant to form a sinker region to totally enclose the PMOS device shown in FIG. 6, thereby avoiding both lateral and vertical parasitic pnp transistor action. Unlike the high voltage NMOS situation, where the n+ region is used only to reduce resistance in the on-state, the high voltage p-channel with lightly doped drain requires that the n+ sinker region contact the n+ buried layer. Furthermore, the device must be surrounded by both the n+ sinker region and a p+ vertical isolation region so that the device is both complex and large. Where a thicker epi layer is used the n+ sinker region must be replaced by a sinker region having both up-isolation and down-isolation regions; and for even thicker epi layers by a sinker having up-isolation, mid-isolation and down-isolation regions. This requires use of an unreasonable number of masks in the process. A comparison of the number of masks required is shown in Table 1 below. A base process is assumed for a two-mask LOCOS process, well, p+, n+ and P.sub.body masks, polysilicon, contact, metal, passivation, and a drift mask for high voltage.
TABLE 1 ______________________________________ Max Breakdown Voltage JIC PROCESS 60 V 100 V 250 V 500 V ______________________________________ Base Process 11 masks 11 masks 11 masks 11 masks n+ Buried Layer x x x x p+ Isolation: Up x x x Middle x Down x x x x n+ Sinker: Up x x Middle x Down x x x x Total Masks 14 15 16 18 ______________________________________
Because three to seven masks may be required to achieve parasitic-free isolation of complimentary devices at high voltages, a fourth process known as dielectric isolation (DI) provides another process alternative. Dielectric isolation, illustrated in FIG. 7, uses the interior of a specially designed tub, filled with n- single crystal silicon and lined with a thick dielectric layer at the bottom and sides of the tub. The isolated region within the tub is completely free of tub-to-tub parasitics and is ideally suited for high voltage applications. The conventional junction-isolated process sequence is often used to form devices within the tubs, except that the buried layer, isolation and sinker portions of the process are deleted. High-voltage p-channel devices formed using DI are also parasitic-free, as indicated in FIG. 8.
Formation of a dielectrically isolated tub of single crystal silicon is a costly procedure, involving patterning and v-groove etching of silicon, provision of a thick field oxidization, deposition of over 20 mil of polysilicon, and controlled grinding, lapping and polishing of the single crystal silicon to a thickness where each single crystal region is separated by the v-grooves with dielectric edges. Both the polysilicon deposition and the grinding procedures are expensive, however. Because the final wafer thickness is primarily polysilicon, the wafers are more fragile than is a single crystal wafer. As a result, the net cost of DI starting material is two to four times the cost of conventional silicon wafers.
TABLE 2 __________________________________________________________________________ EVALUATION SI JIR JIC DI __________________________________________________________________________ PROCESS substrate doping p- p- p- n epi layer doping p- (optional) n- n none isolation diffusions none p+ down p+ up/down none (oxide) complexity/cost medium medium high high LV CMOS n-channel LDMOS in p sub NMOS in p well NMOS in p well NMOS in p well p-channel PMOS in n well PMOS in n epi PMOS in n epi PMOS in n sub HV n-channel MOS description LDD LDMOS in RESURF NEPI LDMOS/VDMOS w/N + LDMOS/VDMOS w/N + p sub LDMOS B/L B/L BVdss 60 to 1200 V 60 to 1200 V 60 to 600 V 60 to 600 V operation pull down pull down pull down pull down pull up pull up pull up HV p-channel MOS description LDD PMOS in n well LDD PMOS in n.sub.epi LDD PMOS in n.sub.epi LDD PMOS in n sub BV.sub.dss 60 to 200 V 60 V 60 to 600 V 60 to 600 V operation pull up pull up pull up pull up parasitic suppression n+ buried layer/ n+ buried layer/sinker n+ buried layer/sinker oxide isolation sinker (option) __________________________________________________________________________
Table 2 summarizes the four processes discussed thus far.. Although a number of these processes are capable of implementing a high-voltage push-pull output stage using an all n-channel design as shown in FIG. 9A, in practice, the driver circuitry for the pull-up n-channel is slow and complex in order to drive the gate voltage V.sub.g (pull-up) 10 V above the high-voltage supply +HV. Unless such a technique is used, the highest gate voltage available is +HV, and the pull-up n-channel will turn off before the output voltage can reach +HV. FIG. 9B shows a push-pull configuration using true complementary devices. In such devices, the p-channel gate voltage is tied to +HV for its off-state and is pulled down toward ground to turn the device on. No special supply voltages or gate drive schemes are required to implement full rail-to-rail output swing. From Table 2 it is clear that only the complex and costly conventional junction-isolated (JIC) and dielectric isolation (DI) processes are capable of providing complimentary output stages with breakdown voltages above 200 V. Many display driver and switch-mode power supply devices require such capability. What is needed here is a junction-isolated process capable of monolithically integrating parasitic free, high voltage n-channel and p-channel devices in a minimum number of masking steps.
Noyce discloses use of a pair of p-n junctions (reverse biased) to provide an isolation region between semiconductor zones, in U.S. Pat. No. 3,117,260. In U.S. Pat. No. 3,150,299, Noyce discloses use of intrinsic silicon between p type and n type semiconductor material that forms part of an isolation region. These patents do not disclose use of a heavily doped region of a single electrical conductivity type, surrounding an enclosed region on the bottom and sides, to form an enclosed region.
Integrated circuits with isolation regions have been disclosed by Peltzer in U.S. Pat. No. 3,648,125. However, the substrate and covering or epitaxial layer in Peltzer are of different electrical conductivity types, one being p type material and one being n type material. In the Peltzer patent, the isolation regions. are oxidized and the buried layer is spaced apart from the isolation region.